3d3215 monolithic 5-tap 3.3v fixed delay line (series 3d3215) f e a t u r e s p a c k a g e s ? all-silicon, low-power 3.3v cmos technology 8 7 6 5 1 2 3 4 in o2 o4 gnd vdd o1 o3 o5 3d 3215m -x x dip ( 300 m i l ) 1 2 3 4 8 7 6 5 in o2 o4 gnd vdd o1 o3 o5 3d 3215z-x x so ic (150 m il) ? vapor phase, ir and wave solderable ? auto-insertable (dip pkg.) ? low ground bounce noise ? leading- and trailing-edge accuracy ? delay range: 1.5ns through 300ns ? total delay tolerance: 2% or 0.5ns (3.3v, 25c) ? temperature stability : 1% typical (0c-70c) ? vdd stability : 1% typical (3.0v-3.6v) f o r mechanical dimensions, click here . f o r package marking details, click here . ? static idd: 1.3ma typical ? minimum input pulse w i dth: 25% of total delay functional description the 3d3215 5-tap delay line product fa mily consists of fixed-delay 3.3v cmos integrated circuits. ea ch package contains a single delay line, tapped and buffered at 5 points spaced uniformly in time. tap-to- tap (incremental) delay values c an range from 1.5ns through 60ns. the input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. the 3d3215 is 3.3v cmos- compatible and features both rising- and falling-edge accuracy. the all-cmos 3d3215 integrated circuit has been designed as a reliable, economic alternative to hybrid fixed delay lines. it is offered in a standard 8-pin auto-insertable dip and a s pace saving surface mount 8-pin soic. pin descriptions in delay line input o1 tap 1 output (20%) o2 tap 2 output (40%) o3 tap 3 output (60%) o4 tap 4 output (80%) o5 tap 5 output (100%) vdd +3.3 volts gnd ground n/c no connection table 1: part number specifications da sh # dela y specifica t io ns input restrictio ns r e c o m m e n d e d a b s o l u t e 3d3215z-xx 3d3215m-xx tota l dela y (ns) ta p-ta p dela y (ns) max freq min p.w. max freq min p.w. -1.5 6.0 0.5* 1.5 0.7 23.8 mhz 21.0 ns 83.3 mhz 6.00 ns -2 8.0 0.5* 2.0 0.8 20.8 mhz 24.0 ns 83.3 mhz 6.00 ns -2.5 10.0 0.5* 2.5 1.0 18.5 mhz 27.0 ns 66.7 mhz 7.50 ns -3 12.0 0.5* 3.0 1.3 16.7 mhz 30.0 ns 55.6 mhz 9.00 ns -4 16.0 0.5* 4.0 1.3 13.9 mhz 36.0 ns 50.0 mhz 10.00 ns -5 20.0 0.5* 5.0 1.4 11.9 mhz 42.0 ns 40.0 mhz 12.50 ns -6 24.0 0.5* 6.0 1.4 10.4 mhz 48.0 ns 55.6 mhz 9.00 ns -8 40.0 0.8 8.0 1.4 8.33 mhz 60.0 ns 41.7 mhz 12.00 ns -10 50.0 1.0 10.0 1.5 6.67 mhz 75.0 ns 40.0 mhz 12.50 ns -12 60.0 1.2 12.0 1.5 5.56 mhz 90.0 ns 33.3 mhz 15.00 ns -15 75.0 1.5 15.0 1.5 4.42 mhz 113 ns 26.7 mhz 18.75 ns -20 100 2.0 20.0 2.0 3.33 mhz 150 ns 20.0 mhz 25.00 ns -25 125 2.5 25.0 2.5 2.66 mhz 188 ns 16.0 mhz 31.25 ns -30 150 3.0 30.0 3.0 2.22 mhz 225 ns 13.3 mhz 37.50 ns -40 200 4.0 40.0 4.0 1.67 mhz 300 ns 10.0 mhz 50.00 ns -50 250 5.0 50.0 5.0 1.33 mhz 375 ns 8.0 mhz 62.50 ns -60 300 6.0 60.0 6.0 1.11 mhz 450 ns 6.7 mhz 75.00 ns * total delay referenced to tap1 output; input-to-tap1 = 7.5ns 1.5ns note: a n y dash number betw een 1.5 and 60 not show n is also av ailable as standard ? 2001 data delay dev i ces doc #01014 data delay devices, inc. 1 12/3/01 3 mt. prospect ave. clifton, nj 07013
3d3215 application notes delay accuracy is guaranteed. to guarantee the table 1 delay accuracy for input frequencies higher than the recommended maximum frequency, the 3d3215 must be tested at the user operating frequency. t herefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. the programmed delay accuracy of the device is guaranteed, t herefore, only at the user specified input frequency. small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy , if at all. nev e rtheless, it is strongly recommended that the engineering staff at data delay devices be consulted. operational description the 3d3215 five-tap delay line architecture is shown in figure 1. the delay line is composed of a number of delay cells connected in series. each delay cell produces at its output a replica of the signal present at its input, shifted in time. the delay cells are matched and share the same compensation signals, which minimizes tap-to- tap delay deviations over temperature and supply voltage variations. input signal characteristics the frequency and/or pulse width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. the reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. therefore a recommended maximum and an absolute maximum operating input frequency and a recommended minimum and an absolute minimum operating pulse width have been specified. operating pulse width the absolute minimum pulse width (high or low) specification, tabulated in table 1, determines the smallest pulse width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. operating frequency the recommended minimum pulse width (high or low) specification determines the smallest pulse width of the delay line input signal for which the output delay accuracy tabulated in table 1 is guaranteed. the absolute maximum frequency specification, tabulated in table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. to guarantee the table 1 delay accuracy for input pulse width smaller than the recommended minimum pulse width, the 3d3215 must be tested at the user operating pulse width. therefore, to facilitate production and device the recommended maximum frequency specification determines the highest frequency of the delay line input signal for which the output vdd o1 in o2 o3 o4 t e m p & vdd c o m pen s a t i o n gnd f i g u r e 1: 3d3 215 f u n c t i o n al diag r a m 25% 25% 25% 25% o5 vdd o1 in o2 o3 o4 tem p & v d d c o m p en s a ti on gnd 20% 20 % 20 % 20 % 20 % o5 d a s h numb e rs < 8 d a s h numb e r s >= 8 doc #01014 data delay devices, inc. 2 12/3/01 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3d3215 application notes (cont?d) identification, the part number will include a custom reference designator identifying the intended frequency and duty cycle of operation. the programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy , if at all. nev e rtheless, it is strongly recommended that the engineering staff at data delay devices be consulted. power supply and temperature considerations the delay of cmos integrated circuits is strongly dependent on power supply and temperature. the monolithic 3d3215 delay line utilizes novel and innovative compensation circuitry to minimize the delay variations induced by fluctuations in power s upply and/or temperature. the thermal coefficient is reduced to 200 ppm/c, which is equivalent to a variation, over the 0c- 70c operating range, of 1% or 0.25ns (whichever is greater) from the 25c delay settings. the power supply coefficient is reduced, over the 3.0v-3.6v operating range, to 1% or 1ns (whichever is greater) of the delay settings at the nominal 3.3vdc power supply. the temperature and power supply sensitivities are based on the measured delay of tap 5 with respect to tap 1. the sensitivity of the input-to- tap 1 delay will be somewhat higher, particularly with the smaller dash numbers. it is essential that the pow er supply pin be adequately by passed and filtered. in addition, the pow er bus should be of as low an impedance construction as possible. pow e r planes are preferred. device specifications table 2: absolute maximum ratings p a r a m e t e r s y m b o l m i n m a x u n i t s n o t e s dc supply voltage v dd - 0 . 3 7 . 0 v input pin voltage v in - 0 . 3 v dd +0. 3 v input pin current i in - 1 . 0 1 . 0 m a 2 5 c storage temperature t st rg - 5 5 1 5 0 c lead temperature t lead 3 0 0 c 1 0 s e c table 3: dc electrical characteristics (0c to 70c, 3.0v to 3.6v) p a r a m e t e r s y m b o l m i n t y p m a x u n i t s n o t e s static supply current* i dd 1 . 3 2 . 0 m a v dd = 3.6v high level input voltage v ih 2 . 0 v low level input voltage v il 0 . 8 v high level input current i ih - 0 . 1 0 . 0 0 . 1 a v ih = v dd low level input current i il - 0 . 1 0 . 0 0 . 1 a v il = 0v high level output current i oh - 8 . 0 - 6 . 0 m a v dd = 3.0v v oh = 2.4v low level output current i ol 6 . 0 7 . 5 m a v dd = 3.0v v ol = 0.4v output rise & fall time t r & t f 2 n s c ld = 5 pf *i dd (dy namic) = 5 * c ld * v dd * f input capacitance = 10 pf ty pical w here: c ld = average capacitance load/tap (pf) output load capacitance (c ld ) = 25 pf max f = input frequency (ghz) doc #01014 data delay devices, inc. 3 12/3/01 3 mt. prospect ave. clifton, nj 07013
3d3215 silicon delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c r load : 10k ? 10% supply voltage (vcc): 3.3v 0.1v c load : 5pf 10% input pulse: high = 3.3v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 ? max. 10k ? 470 ? 5pf dev i c e under te s t di gi t a l s c ope rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 1.5 x total delay period: per in = 3.0 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. out 1 out 2 out 4 out 3 out tr i g in re f tr i g f i g u r e 2: t est s e t u p de v i ce unde r t est (d u t ) d i g i t a l sc o pe/ t i m e i n t e rv a l count e r pu l s e ge ne ra t o r com p ut e r sy st em pr in t e r in out 5 figur e 3 : t i m i ng d i a g r a m t pl h t ph l per in pw in t ris e t fa l l 0. 6v 0. 6v 1. 5v 1. 5v 2. 4v 2. 4v 1. 5v 1. 5v v ih v il v oh v ol in p u t s ign a l ou tp u t s ign a l doc #01014 data delay devices, inc. 4 12/3/01 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
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